• Documentation


• NMC Deliverables

Please send any questions to sales@jmichaelrei.com

NMC is a synthesizable Verilog RTL model of a high performance DSP core with VLIW/SIMD architectures. The core includes two main units: 32-bit RISC processor and 64-bit VECTOR co-processor to support vector operations with elements of variable bit length (US Pat. 6539368 B1).

Features:

• silicon proven - (NM6403 DSP);
• scalable DSP performance;
• original instruction set;
• small number of eq. gates (~80.000);
• clock frequency - 123 MHz (8ns instruction cycle time) at 0.25µm CMOS technology;
• strong software development kit;
• PCI evaluation board.

Documentation

NMC Deliverables

Design Database

• Synthesizable RTL Verilog source code model of NMC core
• Install script
• Synopsys DC synthesizer scripts

NMC software development tools

• Professional NMC SDK
• NMC SDK. Programmer's guide
• NMC assembly language overview
• NMC SDK. Load and exchange library
• Application notes with source code examples

Test Suite

• Verilog Behavioral (non-synthesizeable) description which describes test-bench environment and generates the test stimulus to external NMC interfaces (main NMC interfaces, interrupts etc.)
• Test bench for running a compiled/assembled test program from the linker output file format
• Exhaustive test program/vectors - runs all instructions and all modes

Documentation

• A flyer, summarizing the key features of the NMC core
• Technical data sheet, summarizing interfaces, features and performance
• Design documentation including block diagrams
• Functional specification for all external interfaces
• Documentation of the synthesis scripts
• Documentation of debug / test / emulation features

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